The DB0-7 pins, the parallel data inputs, are used to configure the analog output voltage. CS selects the device, and data is loaded into the input registers on the rising edge of WR. The GAIN pin allows the output range to be set at either 0V to VCC or 0V to 2VCC.
Input data to the AD5330 is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin. An asynchronous CLR input resets the contents of the input register and the DAC register to all zeros. The AD5330 also incorporates a power-on reset circuit that ensures that the DAC output powers on to 0V and remains there until valid data is written to the device.
This breadboard friendly board breaks out every necessary pin of the AD5330 to 0.1″ spaced headers. The board includes a decoupling capacitor, but does not do any voltage regulation; voltage supplied to the board should be within the specified range.